The AI Memory Capacity Expansion Race: Citi Sees 2027 Capex Surging 46.5% to $80.4B — the Classic "Everyone Adds at Once" Tell, Offset by a 2028-29 Supply Lag
The late-cycle tell the memory crowd watches for — all three suppliers adding capacity at once into record prices — is now officially in the numbers. The counterargument is that this cycle's supply response is structurally delayed by fab lead times, equipment bottlenecks, and even the Korean power grid.
Citi's Sept 14, 2026 report forecasts global memory capex (DRAM+NAND) rising +46.5% YoY to $80.4B in 2027, accelerating from $54.9B in 2026. DRAM capex +51.6% to $58.6B, led by Samsung ($20.6B), SK Hynix ($17.5B), and Micron ($15.8B); NAND capex +34.2% to $21.8B (Samsung $7.9B, Kioxia $3.7B, SK Hynix $3.1B, SanDisk $2.9B, Micron $2.1B). Citi's own framing: "even substantial investments are unlikely to bridge the supply-demand gap."
The bull math that justifies the spend: DRAM wafer capacity grows only ~8% in 2027 (to 2.295M wpm) because HBM crowds out commodity DRAM — HBM takes 18%/22%/30% of top-3 DRAM wafer input in 2025/2026/2027 per TrendForce. Bit supply +18.8% vs demand +30.2% → DRAM S/D ratio -8.7% in 2027, -9.7% in 2028 (from +0.5% in 2026). HBM S/D: -22% 2026, -21% 2027, deteriorating to -36% in 2028 as ASICs ramp; TSV packaging capacity 420K → 700K wpm. NAND wafer capacity +3.2% in 2027 — Samsung's NAND capacity actually declines 4.7%. Citi extends the shortage to 2031 on "continual learning" demand (token usage +2,434% YoY in Aug 2026, 31% MoM compound growth).
The supply lag is physical, not just financial: SK Hynix's 54.3T won (~$38.3B) Yongin bet targets its first cleanroom only in June 2029 (per an earlier roadmap; Phase 1 equipment install from early 2027); its $4B+ Indiana HBM fab opened groundbreaking Aug 27, 2026 with cleanroom target Oct 2028 and volume output 2H 2029. The ASML bottleneck binds hardest: EUV output of ~70 tools/year is sold out through 2030, and ASML pushed through an unprecedented mid-lifecycle 10% price increase that triggered follow-on hikes from Lam, Applied Materials, and TEL (see Semiconductor Equipment Leaders Reap Record Revenues from the AI Memory Capex Boom). Korea's KEPCO is even demanding prepayment from memory giants because the national grid can't support new fab construction — "what stops the AI memory boom might have nothing to do with chips." SK Hynix is also in first-ever talks to lease part of Intel's Ohio complex for US memory production.
The market's verdict is already softening: Micron trades at $1,015.80 — 16.3% below its 52-week high and -3.1% over three months — despite a $1.15T market cap, 72.6% gross margins, and four straight beats. SK Hynix's ADR is at 11.4x P/E, Micron at 22.9x. The market is applying classic cycle-peak multiples to peak earnings: low P/E because nobody believes the EPS is durable. Both crossed $1T market cap within weeks of each other, alongside Samsung.
What it means: the "everyone adds capacity at once" tell is present in the 2027 capex numbers (+46.5% in one year), but the bust requires the supply to actually land — and 2028-29 is when Yongin, Indiana, and the 2027-vintage wafer starts all arrive together. If AI demand is still compounding then, the deficit story holds; if token growth mean-reverts, the industry meets a wall of bit supply into a falling market. That collision window — late 2027 through 2029 — is where this cycle turns.1 Watch the capex numbers against DRAM/NAND Contract Pricing: Deceleration Arc Extends — 4Q26 +10-15% DRAM / +15-20% NAND, While the Consumer Side Already Bends for the first sign demand can't absorb the adds.
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An instance of Fab lead times, not price signals, now schedule the memory cycle's turn. — Even a +46.5% synchronized capex surge lands supply only when Yongin, Indiana, and the 2027-vintage wafer starts mature, because EUV is sold out through 2030 and the power grid itself now throttles fab construction. ↩︎