CXMT Arrives as the Swing Supplier: 4F² DDR5 RDIMMs by End-2026, Half-Price DDR4, and a Talent War

CXMT Arrives as the Swing Supplier: 4F² DDR5 RDIMMs by End-2026, Half-Price DDR4, and a Talent War

On Oct 12, Samsung fell 3.6% (to ₩252,500) and SK Hynix 3.4% (to ₩1,624,000) after China's ChangXin Memory Technologies (CXMT) reported "key progress on a so-called 4F² memory-cell structure that is also being pursued by Samsung and SK Hynix" — a cell design that fits more memory cells per chip. CXMT's approach uses "a proprietary Vertical Surrounding Gate transistor, which uses a vertical gate architecture to reduce current leakage while shrinking the area occupied by each memory cell" (Investing.com via Yahoo). CXMT President Cao Kanyu said the company "planned to introduce a new generation of DDR5 registered dual in-line memory modules (RDIMMs) based on the technology by the end of 2026" — aimed at enterprise servers, the exact segment where LTA-priced conventional DRAM is being allocated.

The context that makes this a cycle story, not a tech-launch story:

• CXMT has already started mass production of its fifth-generation (G5) DRAM platform and by industry estimates circulating in early October holds roughly 9–10% of global DRAM bit share, ranked fourth behind the big three.
• It is price-undercutting the incumbents in the commodity segment: 32GB DDR4-3200 ECC modules at $138 — "less than half what Samsung and Micron charge for comparable server" memory¹ (XDA).
• Substitution is already happening at the margin. Summit Insights' Kinngai Chan: "Our industry checks indicate that an increasing number of OEMs and ODMs are adopting Chinese DRAM and NAND" (Reuters via Asahi).
• The incumbents are responding like incumbents at a peak — with money: Samsung is offering up to $560,000 in retention bonuses to keep chip engineers from CXMT poaching (SammyFans, Oct 10). SK Hynix published its own 4F² roadmap in 2025; Samsung targets sub-10nm 4F² mass production by 2028.
• The counterweight: Futurum's Rolf Bulk — "CXMT is still two to three generations behind SK Hynix, Samsung, and Micron when it comes to the performance of their chips," with higher per-chip costs.

What it means: every memory cycle ends with swing supply arriving into record prices, and this cycle's swing producer is Chinese. CXMT's bits land in commodity DDR4/DDR5 exactly where three other brakes are already applied — LTA price ceilings, suppliers deliberately throttling increases to avoid demand destruction, and flat spot trading (DRAM/NAND Contract Pricing: The Deceleration Arc Is Now the Consensus — Q2 +60% → Q4 +10–15%, LTA Ceilings Binding, Spot Flat). CXMT won't touch HBM4 economics for years, but it caps the commodity tail and hands price-sensitive OEMs an exit ramp — the demand-side elasticity that ends every memory cycle. The watch item: whether CXMT's end-2026 DDR5 RDIMMs actually qualify with hyperscaler/server customers, which would move this from headline risk to allocation risk.